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general description the MAX1198 is a 3.3v, dual, 8-bit analog-to-digital con- verter (adc) featuring fully differential wideband track- and-hold (t/h) inputs, driving two adcs. the MAX1198 is optimized for low power, small size, and high-dynamic performance for applications in imaging, instrumenta- tion, and digital communications. this adc operates from a single 2.7v to 3.6v supply, consuming only 264mw, while delivering a typical signal-to-noise and distortion (sinad) of 48.1db at an input frequency of 50mhz and a sampling rate of 100msps. the t/h-driven input stages incorporate 400mhz (-3db) input ampli- fiers. the converters may also be operated with single- ended inputs. in addition to low operating power, the MAX1198 features a 3.2ma sleep mode, as well as a 0.15? power-down mode to conserve power during idle periods. an internal 2.048v precision bandgap reference sets the full-scale range of the adc. a flexible reference structure allows the use of this internal or an externally applied reference, if desired, for applications requiring increased accuracy or a different input voltage range. the MAX1198 features parallel, cmos-compatible three- state outputs. the digital output format can be set to two? complement or straight offset binary through a single con- trol pin. the device provides for a separate output power supply of 1.7v to 3.6v for flexible interfacing with various logic families. the MAX1198 is available in a 7mm x 7mm, 48-pin tqfp package, and is specified for the extended industrial (-40? to +85?) temperature range. pin-compatible lower speed versions of the MAX1198 are also available. refer to the max1195 data sheet for 40msps and the max1197 data sheet for 60msps. in addition to these speed grades, this family includes a multiplexed output version (max1196, 40msps), for which digital data is presented time interleaved and on a single, parallel 8-bit output port. for a 10-bit, pin-compatible upgrade, refer to the max1180 data sheet. with the n.c. pins of the MAX1198 internally pulled down to ground, this adc becomes a drop-in replacement for the max1180. applications features single 2.7v to 3.6v operation excellent dynamic performance 48.1db/47.6db sinad at f in = 50mhz/200mhz 66dbc/61.5dbc sfdr at f in = 50mhz/200mhz -72db interchannel crosstalk at f in = 50mhz low power 264mw (normal operation) 10.6mw (sleep mode) 0.5? (shutdown mode) 0.05db gain and ?.1 phase matching wide 1v p-p differential analog input voltage range 400mhz -3db input bandwidth on-chip 2.048v precision bandgap reference user-selectable output format?wo? complement or offset binary pin-compatible 8-bit and 10-bit upgrades available MAX1198 dual, 8-bit, 100msps, 3.3v, low-power adc with internal reference and parallel outputs ________________________________________________________________ maxim integrated products 1 n.c. n.c. ognd ov dd ov dd ognd n.c. n.c. d0b d1b d2b d3b com v dd gnd ina+ ina- v dd gnd inb- inb+ gnd v dd clk 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 tqfp-ep gnd v dd gnd v dd t/b sleep pd oe d7b d6b d5b d4b 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 refn refp refin refout d7a d6a d5a d4a d3a d2a d1a d0a MAX1198 pin configuration ordering information 19-2412; rev 0; 4/02 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. functional diagram and pin compatible upgrades table appear at end of data sheet. * ep = exposed paddle baseband i/q sampling multichannel if sampling ultrasound and medical imaging battery-powered instrumentation wlan, wwan, wll, mmds modems set-top boxes vsat terminals part temp range pin-package MAX1198ecm -40 c to +85 c 48 tqfp-ep*
MAX1198 dual, 8-bit, 100msps, 3.3v, low-power adc with internal reference and parallel outputs 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = 3.3v, ov dd = 2.5v, 0.1f and 2.2f capacitors from refp, refn, and com to gnd; refout connected to refin through a 10k ? resistor, v in = 2v p-p (differential with respect to com), c l = 10pf at digital outputs, f clk = 100mhz, t a = t min to t max , unless otherwise noted. +25 c guaranteed by production test, <+25 c guaranteed by design and characterization. typical values are at t a = +25 c.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd , ov dd to gnd ...............................................-0.3v to +3.6v ognd to gnd.......................................................-0.3v to +0.3v ina+, ina-, inb+, inb- to gnd ...............................-0.3v to v dd refin, refout, refp, refn, com, clk to gnd .................................-0.3v to (v dd + 0.3v) oe , pd, sleep, t/b, d7a d0a, d7b d0b to ognd .............................-0.3v to (ov dd + 0.3v) continuous power dissipation (t a = +70 c) 48-pin tqfp (derate 12.5mw/ c above +70 c).........1000mw operating temperature range ...........................-40 c to +85 c junction temperature ......................................................+150 c storage temperature range .............................-60 c to +150 c lead temperature (soldering, 10s) .................................+300 c parameter symbol conditions min t yp max units dc accuracy resolution 8 bits integral nonlinearity inl f in = 7.5mhz (note 1) 0.3 1 lsb differential nonlinearity dnl f in = 7.5mhz, no missing codes guaranteed (note 1) 0.2 1 lsb offset error 4%fs gain error 4%fs gain temperature coefficient 100 ppm/ c analog input differential input voltage range v diff differential or single-ended inputs 1.0 v common-mode input voltage range v cm v d d / 2 0.2 v input resistance r in switched capacitor load 57 k ? input capacitance c in 5pf conversion rate maximum clock frequency f clk 100 mhz data latency 5 clock cycles dynamic characteristics (f clk = 100mhz, 4096-point fft) f ina or b = 7.5mhz at -1db fs 48.5 f ina or b = 20mhz at -1db fs 47.0 48.3 f ina or b = 50mhz at -1db fs 48.3 signal-to-noise ratio snr f ina or b = 115.1mhz at -1db fs 48.1 db
MAX1198 dual, 8-bit, 100msps, 3.3v, low-power adc with internal reference and parallel outputs _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = 3.3v, ov dd = 2.5v, 0.1f and 2.2f capacitors from refp, refn, and com to gnd; refout connected to refin through a 10k ? resistor, v in = 2v p-p (differential with respect to com), c l = 10pf at digital outputs, f clk = 100mhz, t a = t min to t max , unless otherwise noted. +25 c guaranteed by production test, <+25 c guaranteed by design and characterization. typical values are at t a = +25 c.) parameter symbol conditions min t yp max units f ina or b = 7.5mhz at -1db fs 48.3 f ina or b = 20mhz at -1db fs 46.5 48.2 f ina or b = 50mhz at -1db fs 48.1 signal-to-noise and distortion sinad f ina or b = 115.1mhz at -1db fs 48 db f ina or b = 7.5mhz at -1db fs 67 f ina or b = 20mhz at -1db fs 60 67 f ina or b = 50mhz at -1db fs 66 spurious-free dynamic range sfdr f ina or b = 115.1mhz at -1db fs 65 dbc f ina or b = 7.5mhz at -1db fs - 67 f ina or b = 20mhz at -1db fs - 67 f ina or b = 50mhz at -1db fs - 67 third-harmonic distortion hd3 f ina or b = 115.1mhz at -1db fs - 66 dbc intermodulation distortion (first five odd-order imds) imd f in1(a or b) = 1.989mhz at -7db fs f in2(a or b) = 2.038mhz at -7db fs (note 2) - 69.5 dbc third-order intermodulation distortion im3 f in1(a or b) = 1.989mhz at -7db fs f in2(a or b) = 2.038mhz at -7db fs (note 2) - 80 dbc f ina or b = 7.5mhz at -1db fs - 66 f ina or b = 20mhz at -1db fs - 67 - 57 f ina or b = 50mhz at -1db fs - 64 total harmonic distortion (first four harmonics) thd f ina or b = 115.1mhz at -1db fs - 58 dbc small-signal bandwidth input at -20db fs, differential inputs 500 mhz full-power bandwidth fpbw input at -1db fs, differential inputs 400 mhz gain flatness (12mhz spacing) f in1(a or b) = 106mhz at -1db fs f in2(a or b) = 118mhz at -1db fs (note 3) 0.05 db aperture delay t ad 1ns aperture jitter t aj 1db snr degradation at nyquist 2 ps rms overdrive recovery time for 1.5 full-scale input 2 ns in t er n a l ref er en c e ( re fin = re fou t thr oug h 10k ? r esi stor ; re fp , re fn , and c om l evel s ar e g ener ated i nter nal l y.) reference output voltage v refout (note 4) 2.048 3% v positive reference output voltage v refp (note 5) 2.162 v negative reference output voltage v refn (note 5) 1.138 v common-mode level v com (note 5) v d d / 2 0.1 v
MAX1198 dual, 8-bit, 100msps, 3.3v, low-power adc with internal reference and parallel outputs 4 _______________________________________________________________________________________ parameter symbol conditions min t yp max units differential reference output voltage range ? v ref ? v ref = v refp - v refn 1.024 3% v reference temperature coefficient tc ref 100 ppm/ c buffered external reference (v refin = 2.048v) positive reference output voltage v refp (note 5) 2.162 v negative reference output voltage v refn (note 5) 1.138 v common-mode level v com (note 5) v d d / 2 0.1 v differential reference output voltage range ? v ref ? v ref = v refp - v refn 1.024 2% v refin resistance r refin > 50 m ? maximum refp, com source current i source 5ma maximum refp, com sink current i sink - 250 a maximum refn source current i source 250 a maximum refn sink current i sink - 5ma u n b u f f er ed ext er n a l r ef er en c e ( v re f in = agn d , r efer ence vol tag e ap p l i ed to re fp , re fn , and c om ) refp, refn input resistance r refp , r refn measured between refp, com, refn, and com 4k ? refp, refn, com input capacitance c in 15 pf differential reference input voltage range ? v ref ? v ref = v refp - v refn 1.024 10% v com input voltage range v com v d d / 2 5% v refp input voltage v refp v c om + ? v re f / 2 v refn input voltage v refn v c om - ? v re f / 2 v digital inputs (clk, pd, oe , sleep, t/b) clk 0.8 v dd input high threshold v ih pd, oe , sleep, t/b 0.8 ov dd v electrical characteristics (continued) (v dd = 3.3v, ov dd = 2.5v, 0.1f and 2.2f capacitors from refp, refn, and com to gnd; refout connected to refin through a 10k ? resistor, v in = 2v p-p (differential with respect to com), c l = 10pf at digital outputs, f clk = 100mhz, t a = t min to t max , unless otherwise noted. +25 c guaranteed by production test, <+25 c guaranteed by design and characterization. typical values are at t a = +25 c.)
MAX1198 dual, 8-bit, 100msps, 3.3v, low-power adc with internal reference and parallel outputs _______________________________________________________________________________________ 5 parameter symbol conditions min t yp max units clk 0.2 v dd input low threshold v il pd, oe , sleep, t/b 0.2 ov dd v input hysteresis v hyst 0.15 v i ih v ih = v dd = ov dd 20 input leakage i il v il = 0 20 a input capacitance c in 5pf digital outputs ( d7a d0a, d7b d0b) output voltage low v ol i sink = -200a 0.2 v output voltage high v oh i source = 200a ov dd - 0.2 v three-state leakage current i leak oe = ov dd 10 a three-state output capacitance c out oe = ov dd 5pf power requirements analog supply voltage range v dd 2.7 3.3 3.6 v output supply voltage range ov dd c l = 15pf 1.7 2.5 3.6 v operating, f ina & b = 20mhz at -1db fs applied to both channels 80 95 sleep mode 3.2 ma analog supply current i vdd shutdown, clock idle, pd = oe = ov dd 0.15 20 a operating, f ina & b = 20mhz at -1db fs applied to both channels (note 6) 11.5 ma sleep mode 2 output supply current i ovdd shutdown, clock idle, pd = oe = ov dd 210 a operating, f ina & b = 20mhz at -1db fs applied to both channels 264 314 sleep mode 10.6 mw analog power dissipation pdiss shutdown, clock idle, pd = oe = ov dd 0.5 66 w offset, v dd 5% 3 power-supply rejection psrr gain, v dd 5% 3 mv/v timing characteristics clk rise to output data valid time t do c l = 20pf (notes 1, 7) 6 8.25 ns oe fall to output enable time t enable 5ns oe rise to output disable time t disable 5ns clk pulse width high t ch clock period: 10ns (note 7) 5 0.5 ns clk pulse width low t cl clock period: 10ns (note 7) 5 0.5 ns electrical characteristics (continued) (v dd = 3.3v, ov dd = 2.5v, 0.1f and 2.2f capacitors from refp, refn, and com to gnd; refout connected to refin through a 10k ? resistor, v in = 2v p-p (differential with respect to com), c l = 10pf at digital outputs, f clk = 100mhz, t a = t min to t max , unless otherwise noted. +25 c guaranteed by production test, <+25 c guaranteed by design and characterization. typical values are at t a = +25 c.)
MAX1198 dual, 8-bit, 100msps, 3.3v, low-power adc with internal reference and parallel outputs 6 _______________________________________________________________________________________ note 1: guaranteed by design. not subject to production testing. note 2: intermodulation distortion is the total power of the intermodulation products relative to the total input power. note 3: analog attenuation is defined as the amount of attenuation of the fundamental bin from a converted fft between two applied input signals with the same magnitude (peak-to-peak) at f in1 and f in2 . note 4: refin and refout should be bypassed to gnd with a 0.1f (min) and 2.2f (typ) capacitor. note 5: refp, refn, and com should be bypassed to gnd with a 0.1f (min) and 2.2f (typ) capacitor. note 6: typical analog output current at f ina & b = 20mhz. for digital output currents vs. analog input frequency, see typical operating characteristics . note 7: see figure 3 for detailed system timing diagrams. clock to data valid timing is measured from 50% of the clock level to 50% of the data output level. note 8: crosstalk rejection is tested by applying a test tone to one channel and holding the other channel at dc level. crosstalk is measured by calculating the power ratio of the fundamental of each channel s fft. note 9: amplitude matching is measured by applying the same signal to each channel and comparing the magnitude of the funda- mental of the calculated fft. note 10: phase matching is measured by applying the same signal to each channel and comparing the phase of the fundamental of the calculated fft. the data from both adc channels must be captured simultaneously during this test. note 11: sinad settles to within 0.5db of its typical value in unbuffered external reference mode. parameter symbol conditions min t yp max units wake up from sleep mode 1 wake-up time t wake wake up from shutdown mode (note 11) 20 s channel-to-channel matching crosstalk f ina or b = 20mhz at -1db fs (note 8) - 72 db gain matching f ina or b = 20mhz at -1db fs (note 9) 0.05 db phase matching f ina or b = 20mhz at -1db fs (note 10) 0.1 degrees electrical characteristics (continued) (v dd = 3.3v, ov dd = 2.5v, 0.1f and 2.2f capacitors from refp, refn, and com to gnd; refout connected to refin through a 10k ? resistor, v in = 2v p-p (differential with respect to com), c l = 10pf at digital outputs, f clk = 100mhz, t a = t min to t max , unless otherwise noted. +25 c guaranteed by production test, <+25 c guaranteed by design and characterization. typical values are at t a = +25 c.)
MAX1198 dual, 8-bit, 100msps, 3.3v, low-power adc with internal reference and parallel outputs _______________________________________________________________________________________ 7 typical operating characteristics (v dd = 3.3v, ov dd = 2.5v, v refin = 2.048v, differential input at -1db fs, f clk = 100mhz, c l 10pf, t a = +25 c, unless otherwise noted.) sfdr (dbc) 48 56 64 72 80 40 spurious-free dynamic range vs. analog input frequency MAX1198 toc09 analog input frequency (mhz) 160 120 80 40 0200 chb cha thd (dbc) -72 -64 -56 -48 -40 -80 total harmonic distortion vs. analog input frequency MAX1198 toc08 analog input frequency (mhz) 160 120 80 40 0200 chb cha signal-to-noise + distortion vs. analog input frequency MAX1198 toc07 analog input frequency (mhz) snr (db) 160 120 80 40 42 44 46 48 50 40 0200 chb cha signal-to-noise ratio vs. analog input frequency MAX1198 toc06 analog input frequency (mhz) snr (db) 160 120 80 40 42 44 46 48 50 40 0200 cha chb MAX1198 toc05 12 11 10 9 8 713 two-tone imd plot (differential input, 8192-point data record) analog input frequency (mhz) amplitude (db) -80 -70 -60 -50 -40 -30 -20 -10 0 -90 f clk = 100.007936mhz f in1 = 10.022768mhz f in2 = 10.047184mhz ain = -7db fs coherent sampling f in1 f in2 two-tone imd plot (differential input, 8192-point data record) MAX1198 toc04 4.5 4.0 3.0 3.5 1.0 1.5 2.0 2.5 0.5 0 5.0 analog input frequency (mhz) amplitude (db) -80 -70 -60 -50 -40 -30 -20 -10 0 -90 f clk = 100.007936mhz f in1 = 1.989904mhz f in2 = 2.038736mhz ain = -7db fs coherent sampling f in1 f in2 MAX1198 toc03 fft plot cha (differential input, 8192-point data record) analog input frequency (mhz) amplitude (db) 45 40 30 35 10 15 20 25 5 -80 -70 -60 -50 -40 -30 -20 -10 0 -90 050 f clk = 100.050607mhz f ina = 114.9629350mhz f inb = 99.5010126mhz ain = -1db fs coherent sampling f inb f ina hd2 hd3 fft plot cha (differential input, 8192-point data record) MAX1198 toc02 analog input frequency (mhz) amplitude (db) 45 40 30 35 10 15 20 25 5 -80 -70 -60 -50 -40 -30 -20 -10 0 -90 050 f clk = 100.050607mhz f ina = 49.7443997mhz f inb = 19.8708908mhz ain = -1db fs coherent sampling f inb f ina hd2 hd3 fft plot cha (differential input, 8192-point data record) MAX1198 toc01 analog input frequency (mhz) amplitude (db) 45 40 30 35 10 15 20 25 5 -80 -70 -60 -50 -40 -30 -20 -10 0 -90 050 f clk = 100.050607mhz f ina = 19.8708908mhz f inb = 7.5355498mhz ain = -1db fs coherent sampling f inb f ina hd2 hd3
MAX1198 dual, 8-bit, 100msps, 3.3v, low-power adc with internal reference and parallel outputs 8 _______________________________________________________________________________________ typical operating characteristics (continued) (v dd = 3.3v, ov dd = 2.5v, v refin = 2.048v, differential input at -1db fs, f clk = 100mhz, c l 10pf, t a = +25 c, unless otherwise noted.) differential nonlinearity (262144-point data record) MAX1198 toc18 digital output code dnl (lsb) 224 192 128 160 64 98 32 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0256 integral nonlinearity (262144-point data record) MAX1198 toc17 digital output code inl (lsb) 224 192 128 160 64 98 32 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0256 MAX1198 toc16 input power (db fs) sfdr (dbc) -4 -8 -12 -16 50 55 60 65 70 75 45 -20 0 spurious-free dynamic range vs. input power (f in = 19.87089082mhz) MAX1198 toc15 input power (db fs) thd (dbc) -4 -8 -12 -16 -70 -65 -60 -55 -50 -45 -75 -20 0 total harmonic distortion vs. input power (f in = 19.87089082mhz) signal-to-noise + distortion vs. input power (f in = 19.87089082mhz) MAX1198 toc14 input power (db fs) sinad (db) -4 -8 -12 -16 30 35 40 45 50 55 25 -20 0 signal-to-noise ratio vs. input power (f in = 19.87089082mhz) MAX1198 toc13 input power (db fs) snr (db) -4 -8 -12 -16 30 35 40 45 50 55 25 -20 0 small-signal input bandwidth vs. analog input frequency, differential MAX1198 toc12 analog input frequency (mhz) gain (db) 100 10 -3 -2 -1 0 1 2 -4 1 1000 v in = 100mv p-p full-power input bandwidth vs. analog input frequency, differential MAX1198 toc11 analog input frequency (mhz) gain (db) 100 10 -4 -3 -2 -1 0 1 -5 11000 snr/sinad, thd/sfdr vs. temperature MAX1198 toc10 temperature ( c) snr/sinad, thd/sfdr (db, dbc) 60 35 10 -15 40 50 60 70 80 90 30 -40 85 snr sinad sfdr thd f in = 19.87089082mhz
MAX1198 dual, 8-bit, 100msps, 3.3v, low-power adc with internal reference and parallel outputs _______________________________________________________________________________________ 9 typical operating characteristics (continued) (v dd = 3.3v, ov dd = 2.5v, v refin = 2.048v, differential input at -1db fs, f clk = 100mhz, c l 10pf, t a = +25 c, unless otherwise noted.) internal reference voltage vs. temperature MAX1198 toc26 temperature ( c) v refout (v) 60 35 10 -15 2.0340 2.0380 2.0420 2.0460 2.0500 2.0300 -40 85 internal reference voltage vs. analog supply voltage MAX1198 toc25 v dd (v) v refout (v) 3.45 3.30 3.15 3.00 2.85 2.0405 2.0410 2.0415 2.0420 2.0425 2.0430 2.0400 2.70 3.60 snr/sinad, thd/sfdr vs. clock duty cycle MAX1198 toc24 clock duty cycle (%) snr/sinad, thd/sfdr (db, dbc) 56 52 48 44 40 50 sfdr thd sinad snr 60 70 80 30 40 60 f in = 19.87089082mhz digital supply current vs. analog input frequency MAX1198 toc23 analog input frequency (mhz) i ovdd (ma) 40 30 20 10 4 8 12 16 20 0 050 analog supply current vs. temperature MAX1198 toc22 temperature ( c) i vdd (ma) 60 35 10 -15 74 78 82 86 90 70 -40 85 snr/sinad, thd/sfdr vs. sampling speed MAX1198 toc21 sampling speed (msps) snr/sinad, thd/sfdr (db, dbc) 100 80 60 40 20 48 56 64 sfdr snr sinad thd 72 80 40 0120 f in = 19.87089082mhz offset error vs. temperature, external reference v refin = 2.048v MAX1198 toc20 temperature ( c) offset error (%fs) 60 35 10 -15 -0.7 -0.2 0.3 0.8 -1.2 cha -40 85 chb gain error vs. temperature, external reference v refin = 2.048v MAX1198 toc19 temperature ( c) gain error (%fs) 60 35 10 -15 -0.1 0.1 0.3 0.5 -0.3 -40 85 chb cha
MAX1198 dual, 8-bit, 100msps, 3.3v, low-power adc with internal reference and parallel outputs 10 ______________________________________________________________________________________ pin description pin name function 1 com common-mode voltage i/o. bypass to gnd with a 0.1f capacitor. 2, 6, 11, 14, 15 v dd analog supply voltage. bypass to gnd with a capacitor combination of 2.2f in parallel with 0.1f. 3, 7, 10, 13, 16 gnd analog ground 4 ina+ channel a positive analog input. for single-ended operation connect signal source to ina+. 5 ina- channel a negative analog input. for single-ended operation connect ina- to com. 8 inb- channel b negative analog input. for single-ended operation connect inb- to com. 9 inb+ channel b positive analog input. for single-ended operation connect signal source to inb+. 12 clk converter clock input 17 t/b t/b selects the adc digital output format high: two s complement low: straight offset binary 18 sleep sleep mode input high: disables both quantizers, but leaves the reference bias circuit active low: normal operation 19 pd active-high power-down input high: power-down mode low: normal operation 20 oe active-low output enable input high: digital outputs disabled low: digital outputs enabled 21 d7b three-state digital output, bit 7 (msb), channel b 22 d6b three-state digital output, bit 6, channel b 23 d5b three-state digital output, bit 5, channel b 24 d4b three-state digital output, bit 4, channel b 25 d3b three-state digital output, bit 3, channel b 26 d2b three-state digital output, bit 2, channel b 27 d1b three-state digital output, bit 1, channel b 28 d0b three-state digital output, bit 0, channel b 29, 30, 35, 36 n.c. no connection 31, 34 ognd output driver ground 32, 33 ov dd output driver supply voltage. bypass to ognd with a capacitor combination of 2.2f in parallel with 0.1f. 37 d0a three-state digital output, bit 0, channel a 38 d1a three-state digital output, bit 1, channel a 39 d2a three-state digital output, bit 2, channel a 40 d3a three-state digital output, bit 3, channel a 41 d4a three-state digital output, bit 4, channel a
detailed description the MAX1198 uses a seven-stage, fully differential pipelined architecture (figure 1) that allows for high- speed conversion while minimizing power consump- tion. samples taken at the inputs move progressively through the pipeline stages every half-clock cycle. including the delay through the output latch, the total clock-cycle latency is five clock cycles. flash adcs convert the held input voltages into a digi- tal code. internal mdacs convert the digitized results back into analog voltages, which are then subtracted from the original held input signals. the resulting error signals are then multiplied by two, and the residues are passed along to the next pipeline stages where the process is repeated until the signals have been processed by all seven stages. input track-and-hold (t/h) circuits figure 2 displays a simplified functional diagram of the input t/h circuits in both track and hold mode. in track mode, switches s1, s2a, s2b, s4a, s4b, s5a, and s5b MAX1198 dual, 8-bit, 100msps, 3.3v, low-power adc with internal reference and parallel outputs ______________________________________________________________________________________ 11 pin description (continued) pin name function 42 d5a three-state digital output, bit 5, channel a 43 d6a three-state digital output, bit 6, channel a 44 d7a three-state digital output, bit 7 (msb), channel a 45 refout internal reference voltage output. may be connected to refin through a resistor or a resistor- divider. 46 refin reference input. v refin = 2 x (v refp - v refn ). bypass to gnd with a >0.1f capacitor. 47 refp positive reference i/o. conversion range is (v refp - v refn ). bypass to gnd with a >0.1f capacitor. 48 refn negative reference i/o. conversion range is (v refp - v refn ). bypass to gnd with a >0.1f capacitor. 8 v ina stage 1 stage 2 d7a?0a v ina = input voltage between ina+ and ina- (differential or single ended) v inb = input voltage between inb+ and inb- (differential or single ended) digital alignment logic stage 6 stage 7 2-bit flash adc t/h 8 v inb stage 1 stage 2 d7b?0b digital alignment logic stage 6 stage 7 2-bit flash adc t/h figure 1. pipelined architecture?tage blocks
MAX1198 are closed. the fully differential circuits sample the input signals onto the two capacitors (c2a and c2b) through switches s4a and s4b. s2a and s2b set the common mode for the amplifier input, and open simul- taneously with s1 sampling the input waveform. switches s4a, s4b, s5a, and s5b are then opened before switches s3a and s3b connect capacitors c1a and c1b to the output of the amplifier and switch s4c is closed. the resulting differential voltages are held on capacitors c2a and c2b. the amplifiers are used to charge capacitors c1a and c1b to the same values originally held on c2a and c2b. these values are then presented to the first-stage quantizers and isolate the pipelines from the fast-changing inputs. the wide input bandwidth t/h amplifiers allow the MAX1198 to track and sample/hold analog inputs of high frequencies (>nyquist). both adc inputs (ina+, inb+ and ina-, inb-) can be driven either differentially or single ended. dual, 8-bit, 100msps, 3.3v, low-power adc with internal reference and parallel outputs 12 ______________________________________________________________________________________ s3b s3a com s5b s5a inb+ inb- s1 out out c2a c2b s4c s4a s4b c1b c1a internal bias internal bias com hold hold clk internal nonoverlapping clock signals track track s2a s2b s3b s3a com s5b s5a ina+ ina- s1 out out c2a c2b s4c s4a s4b c1b c1a internal bias internal bias com s2a s2b MAX1198 figure 2. MAX1198 t/h amplifiers
match the impedance of ina+ and ina-, as well as inb+ and inb-, and set the common-mode voltage to mid supply (v dd /2) for optimum performance. analog inputs and reference configurations the full-scale range of the MAX1198 is determined by the internally generated voltage difference between refp (v dd /2 + v refin /4) and refn (v dd /2 - v refin /4). the full-scale range for both on-chip adcs is adjustable through the refin pin, which is provided for this purpose. the MAX1198 provides three modes of reference operation: internal reference mode buffered external reference mode unbuffered external reference mode in internal reference mode, connect the internal refer- ence output refout to refin through a resistor (e.g., 10k ? ) or resistor-divider, if an application requires a reduced full-scale range. for stability and noise-filtering purposes, bypass refin with a >10nf capacitor to gnd. in internal reference mode, refout, com, refp, and refn become low-impedance outputs. in buffered external reference mode, adjust the refer- ence voltage levels externally by applying a stable and accurate voltage at refin. in this mode, com, refp, and refn are outputs. refout can be left open or connected to refin through a >10k ? resistor. in unbuffered external reference mode, connect refin to gnd. this deactivates the on-chip reference buffers for refp, com, and refn. with their buffers shut down, these nodes become high-impedance inputs and can be driven through separate, external reference sources. for detailed circuit suggestions and how to drive this dual adc in buffered/unbuffered external reference mode, see the applications information section. clock input (clk) the MAX1198 s clk input accepts a cmos-compati- ble clock signal. since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (<2ns). in particular, sampling occurs on the rising edge of the clock signal, requiring this edge to provide lowest possible jitter. any significant aperture jitter would limit the snr perfor- mance of the on-chip adcs as follows: where f in represents the analog input frequency and t aj is the time of the aperture jitter. clock jitter is especially critical for undersampling applications. the clock input should always be consid- ered as an analog input and routed away from any ana- log input or other digital signal lines. snr ft in aj log = 20 1 2 MAX1198 dual, 8-bit, 100msps, 3.3v, low-power adc with internal reference and parallel outputs ______________________________________________________________________________________ 13 n - 6 n n - 5 n + 1 n - 4 n + 2 n - 3 n + 3 n - 2 n + 4 n - 1 n + 5 n n + 6 n + 1 5-clock-cycle latency analog input clock input data output d7a d0a t do t ch t cl n - 6 n - 5 n - 4 n - 3 n - 2 n - 1 n n + 1 data output d7b d0b t ad figure 3. system timing diagram
MAX1198 the MAX1198 clock input operates with a voltage thresh- old set to v dd /2. clock inputs with a duty cycle other than 50% must meet the specifications for high and low periods as stated in the electrical characteristics table . system timing requirements figure 3 depicts the relationship between the clock input, analog input, and data output. the MAX1198 samples at the rising edge of the input clock. output data for channels a and b is valid on the next rising edge of the input clock. the output data has an internal latency of five clock cycles. figure 3 also determines the relationship between the input clock parameters and the valid output data on channels a and b. digital output data (d0a/b?7a/b), output data format selection (t/b), output enable ( oe ) all digital outputs, d0a d7a (channel a) and d0b d7b (channel b), are ttl/cmos-logic compatible. there is a five-clock-cycle latency between any particular sample and its corresponding output data. the output coding can either be straight offset binary or two s com- plement (table 1) controlled by a single pin (t/b). pull t/b low to select offset binary and high to activate two s complement output coding. the capacitive load on the digital outputs d0a d7a and d0b d7b should be kept as low as possible (<15pf), to avoid large digital cur- rents that could feed back into the analog portion of the MAX1198, thereby degrading its dynamic performance. using buffers on the digital outputs of the adcs can fur- ther isolate the digital outputs from heavy capacitive loads. to further improve the dynamic performance of the MAX1198, small-series resistors (e.g., 100 ? ) may be added to the digital output paths close to the MAX1198. figure 4 displays the timing relationship between out- put enable and data output valid, as well as power- down/wakeup and data output valid. power-down and sleep modes the MAX1198 offers two power-save modes sleep mode (sleep) and full power-down (pd) mode. in sleep mode (sleep = 1), only the reference bias circuit is active (both adcs are disabled), and current con- sumption is reduced to 3.2ma. to enter full power-down mode, pull pd high. with oe simultaneously low, all outputs are latched at the last value prior to power-down. pulling oe high forces the digital outputs into a high-impedance state. applications information figure 5 depicts a typical application circuit containing two single-ended-to-differential converters. the internal reference provides a v dd /2 output voltage for level- shifting purposes. the input is buffered and then split to a voltage follower and inverter. one lowpass filter per amplifier suppresses some of the wideband noise associated with high-speed op amps. the user can select the r iso and c in values to optimize the filter per- formance, to suit a particular application. for the appli- cation in figure 5, a r iso of 50 ? is placed before the capacitive load to prevent ringing and oscillation. the 22pf c in capacitor acts as a small filter capacitor. using transformer coupling an rf transformer (figure 6) provides an excellent solution to convert a single-ended source signal to a fully differential signal, required by the MAX1198 for optimum performance. connecting the center tap of the transformer to com provides a v dd /2 dc level shift to the input. although a 1:1 transformer is shown, a step- up transformer can be selected to reduce the drive dual, 8-bit, 100msps, 3.3v, low-power adc with internal reference and parallel outputs 14 ______________________________________________________________________________________ output d7a d0a oe t disable t enable high-z high-z valid data output d7b d0b high-z high-z valid data figure 4. output timing diagram st ra ig ht o f fset b ina r y t wo s c o m pl em en t d iff er en t ial in pu t vo lt a g e* d iff er en t ial in pu t t/b = 0 t/b = 1 v ref x 255/256 +full scale - 1lsb 1111 1111 0111 1111 v ref x 1/256 +1lsb 1000 0001 0000 0001 0 bipolar zero 1000 0000 0000 0000 -v ref x 1/256 -1lsb 0111 1111 1111 1111 -v ref x 255/256 -full scale + 1lsb 0000 0001 1000 0001 -v ref x 256/256 -full scale 0000 0000 1000 0000 table 1. MAX1198 output codes for differential inputs * v ref = v refp - v refn
MAX1198 dual, 8-bit, 100msps, 3.3v, low-power adc with internal reference and parallel outputs ______________________________________________________________________________________ 15 input 300 ? -5v +5v 0.1 f 0.1 f 0.1 f -5v 600 ? 300 ? ina- ina+ lowpass filter com 600 ? +5v -5v 0.1 f 600 ? 300 ? 600 ? 300 ? 0.1 f 0.1 f 0.1 f +5v 0.1 f 300 ? max4108 MAX1198 inb- inb+ max4108 max4108 lowpass filter input 300 ? -5v +5v 0.1 f 0.1 f 0.1 f c in 22pf -5v 600 ? 300 ? lowpass filter 600 ? +5v -5v 0.1 f 600 ? 300 ? 600 ? 300 ? 0.1 f 0.1 f 0.1 f +5v 0.1 f 300 ? max4108 max4108 max4108 lowpass filter r is0 50 ? c in 22pf r is0 50 ? c in 22pf r is0 50 ? c in 22pf r is0 50 ? 300 ? 300 ? figure 5. typical application for single-ended-to-differential conversion
MAX1198 requirements. a reduced signal swing from the input driver, such as an op amp, can also improve the overall distortion. in general, the MAX1198 provides better sfdr and thd with fully differential input signals than single- ended drive, especially for very high input frequencies. in differential input mode, even-order harmonics are lower as both inputs (ina+, ina- and/or inb+, inb-) are balanced, and each of the adc inputs only requires half the signal swing compared to single-ended mode. single-ended ac-coupled input signal figure 7 shows an ac-coupled, single-ended applica- tion. amplifiers like the max4108 provide high speed, high bandwidth, low noise, and low distortion to main- tain the integrity of the input signal. buffered external reference drives multiple adcs multiple-converter systems based on the MAX1198 are well suited for use with a common reference voltage. the refin pin of those converters can be connected directly to an external reference source. a precision bandgap reference like the max6062 gen- erates an external dc level of 2.048v (figure 8), and exhibits a noise-voltage density of 150nv/ hz . its out- put passes through a 1-pole lowpass filter (with 10hz cutoff frequency) to the max4250, which buffers the reference before its output is applied to a second 10hz lowpass filter. the max4250 provides a low offset volt- age (for high gain accuracy) and a low noise level. the passive 10hz filter following the buffer attenuates noise produced in the voltage reference and buffer stages. this filtered noise density, which decreases for higher frequencies, meets the noise levels specified for preci- sion adc operation. dual, 8-bit, 100msps, 3.3v, low-power adc with internal reference and parallel outputs 16 ______________________________________________________________________________________ MAX1198 t1 n.c. v in 6 1 5 2 4 3 22pf 22pf 0.1 f 0.1 f 2.2 f 25 ? 25 ? minicircuits tt1 6-kk81 t1 n.c. v in 6 1 5 2 4 3 22pf 22pf 0.1 f 0.1 f 2.2 f 25 ? 25 ? minicircuits tt1-6-kk81 ina- ina+ inb- inb+ com MAX1198 0.1 f 1k ? 1k ? 100 ? 100 ? c in 22pf c in 22pf inb+ inb- com ina+ ina- 0.1 f r iso 50 ? r iso 50 ? refp refn v in max4108 0.1 f 1k ? 1k ? 100 ? 100 ? c in 22pf c in 22pf 0.1 f r iso 50 ? r iso 50 ? refp refn v in max4108 figure 6. transformer-coupled input drive figure 7. using an op amp for single-ended, ac-coupled input drive
MAX1198 dual, 8-bit, 100msps, 3.3v, low-power adc with internal reference and parallel outputs ______________________________________________________________________________________ 17 unbuffered external reference drives multiple adcs connecting each refin to analog ground disables the internal reference of each device, allowing the internal reference ladders to be driven directly by a set of external reference sources. followed by a 10hz low- pass filter and precision voltage-divider, the max6066 generates a dc level of 2.500v. the buffered outputs of this divider are set to 2.0v, 1.5v, and 1.0v, with an accuracy that depends on the tolerance of the divider resistors. these three voltages are buffered by the max4252, which provides low noise and low dc offset. the indi- vidual voltage followers are connected to 10hz low- pass filters, which filter both the reference voltage and amplifier noise to a level of 3nv/ hz . the 2.0v and 1.0v reference voltages set the differential full-scale range of the associated adcs at 2v p-p . the 2.0v and 1.0v buffers drive the adc s internal ladder resistances between them. note that the common power supply for all active com- ponents removes any concern regarding power-supply sequencing when powering up or down. with the out- puts of the max4252 matching better than 0.1%, the buffers and subsequent lowpass filters can be replicat- ed to support as many as 32 adcs. for applications that require more than 32 matched adcs, a voltage reference and divider string common to all converters is highly recommended. typical qam demodulation application a frequently used modulation technique in digital com- munications applications is quadrature amplitude modulation (qam). typically found in spread-spec- trum-based systems, a qam signal represents a carrier frequency modulated in both amplitude and phase. at the transmitter, modulating the baseband signal with quadrature outputs, a local oscillator followed by sub- sequent upconversion can generate the qam signal. the result is an in-phase (i) and a quadrature (q) carri- er component, where the q component is 90 phase max4250 max6062 16.2k ? 162 ? 3.3v 2 4 2 3 5 10hz lowpass filter 10hz lowpass filter 1 1 refout refp refin 1 f MAX1198 n = 1 refn 29 n.c. 2.048v n.c. 31 32 1 2 29 31 32 1 2 com refout note: one front-end reference circuit design may be used with up to 1000 adcs. refp refin MAX1198 n = 1000 refn com 3 0.1 f 0.1 f 3.3v 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 2.2 f 10v 0.1 f 0.1 f 0.1 f 100 f 0.1 f figure 8. external buffered (max4250) reference drive using a max6062 bandgap reference
MAX1198 shifted with respect to the in-phase component. at the receiver, the qam signal is divided down into its i and q components, essentially representing the modulation process reversed. figure 10 displays the demodulation process performed in the analog domain, using the dual matched 3.3v, 8-bit adc MAX1198 and the max2451 quadrature demodulator to recover and digitize the i and q baseband signals. before being digitized by the MAX1198, the mixed down-signal com- ponents may be filtered by matched analog filters, such as nyquist or pulse-shaping filters, which remove unwanted images from the mixing process, thereby enhancing the overall signal-to-noise (snr) perfor- mance and minimizing intersymbol interference. grounding, bypassing, and board layout the MAX1198 requires high-speed board layout design techniques. locate all bypass capacitors as close to the device as possible, preferably on the same side as the adc, using surface-mount devices for minimum inductance. bypass v dd , refp, refn, and com with two parallel 0.1f ceramic capacitors and a 2.2f bipolar capacitor to gnd. follow the same rules to bypass the digital supply (ov dd ) to ognd. multilayer boards with separated ground and power planes produce the highest level of signal integrity. consider the use of a split ground plane arranged to match the dual, 8-bit, 100msps, 3.3v, low-power adc with internal reference and parallel outputs 18 ______________________________________________________________________________________ 1/4 max4252 max6066 1/4 max4252 1/4 max4252 1.47k ? 21.5k ? 21.5k ? 21.5k ? 21.5k ? 21.5k ? 47 ? 3.3v 3.3v 11 2 2 3 4 1 1 refout refp refin 1 f 10 f 6v MAX1198 n = 1 refn 29 n.c. n.c. 31 32 1 2 29 31 32 1 2 com refout note: one front-end reference circuit design may be used with up to 32 adcs. refp refin MAX1198 n = 32 refn com 2.0v at 8ma 3 0.1 f 0.1 f max4254 power-supply bypassing. place capacitor as close as possible to the op amp. 3.3v 1.47k ? 47 ? 3.3v 1.5v 11 6 5 4 7 10 f 6v 1.5v at 0ma 1.47k ? 47 ? 3.3v 11 9 10 4 8 10 f 6v 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 2.2 f 10v 0.1 f 0.1 f 1.0v at -8ma 330 f 6v 330 f 6v 330 f 6v 2.0v 1.0v figure 9. external unbuffered reference drive with max4252 and max6066
physical location of the analog ground (gnd) and the digital output driver ground (ognd) on the adc s package. the two ground planes should be joined at a single point so the noisy digital ground currents do not interfere with the analog ground plane. the ideal loca- tion for this connection can be determined experimen- tally at a point along the gap between the two ground planes, which produces optimum results. make this connection with a low-value, surface-mount resistor (1 ? to 5 ? ), a ferrite bead, or a direct short. alternatively, all ground pins could share the same ground plane if the ground plane is sufficiently isolated from any noisy, digital systems ground plane (e.g., downstream output buffer or dsp ground plane). route high-speed digital signal traces away from the sensitive analog traces of either channel. make sure to isolate the analog input lines to each respective converter to minimize channel-to-channel crosstalk. keep all signal lines short and free of 90 turns. static parameter definitions integral nonlinearity integral nonlinearity (inl) is the deviation of the values on an actual transfer function from a straight line. this straight line can be either a best-straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. the static linearity parameters for the MAX1198 are mea- sured using the best-straight-line-fit method. differential nonlinearity differential nonlinearity (dnl) is the difference between an actual step width and the ideal value of 1lsb. a dnl error specification of less than 1lsb guarantees no missing codes and a monotonic transfer function. dynamic parameter definitions aperture jitter figure 11 depicts the aperture jitter (t aj ), which is the sample-to-sample variation in the aperture delay. aperture delay aperture delay (t ad ) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (figure 11). signal-to-noise ratio for a waveform perfectly reconstructed from digital samples, the theoretical maximum snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum analog-to-digital noise is caused by quantiza- tion error only and results directly from the adc s reso- lution (n-bits): snr db[max] = 6.02 db ? n + 1.76 db MAX1198 dual, 8-bit, 100msps, 3.3v, low-power adc with internal reference and parallel outputs ______________________________________________________________________________________ 19 0 90 8 downconverter max2451 ina+ MAX1198 ina- inb+ inb- dsp post- processing figure 10. typical qam application using the MAX1198 hold analog input sampled data (t/h) t/h t ad t aj track track clk figure 11. t/h aperture timing
MAX1198 dual, 8-bit, 100msps, 3.3v, low-power adc with internal reference and parallel outputs 20 ______________________________________________________________________________________ in reality, there are other noise sources besides quanti- zation noise: thermal noise, reference noise, clock jitter, etc. snr is computed by taking the ratio of the rms signal to the rms noise, which includes all spectral components minus the fundamental, the first five har- monics, and the dc offset. signal-to-noise plus distortion sinad is computed by taking the ratio of the rms sig- nal to all spectral components minus the fundamental and the dc offset. effective number of bits effective number of bits (enob) specifies the dynamic performance of an adc at a specific input frequency and sampling rate. an ideal adc s error consists of quantization noise only. enob for a full-scale sinusoidal input waveform is computed from: total harmonic distortion thd is typically the ratio of the rms sum of the first four harmonics of the input signal to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 through v 5 are the amplitudes of the 2nd- through 5th-order harmonics. spurious-free dynamic range spurious-free dynamic range (sfdr) is the ratio expressed in decibels of the rms amplitude of the fun- damental (maximum signal component) to the rms value of the next largest spurious component, exclud- ing dc offset. intermodulation distortion the two-tone intermodulation distortion (imd) is the ratio expressed in decibels of either input tone to the worst third-order (or higher) intermodulation products. the individual input tone levels are at -7db full scale and their envelope is at -1db full scale. thd vvvv v log = +++ 20 2 2 3 2 4 2 5 2 1 enob sinad . . = ? 176 602 chip information transistor count: 11,601 process: cmos
MAX1198 dual, 8-bit, 100msps, 3.3v, low-power adc with internal reference and parallel outputs ______________________________________________________________________________________ 21 pin-compatible upgrades (sampling speed and resolution) functional diagram gnd reference output drivers control t/h t/h adc dec output drivers refout refn com refp refin ina+ ina- clk inb+ inb- v dd dec adc ognd ov dd d7a d0a oe d7b d0b t/b pd sleep MAX1198 8 8 8 8 8-bit part 10-bit part sampling speed (msps) max1195 max1183 40 max1197 max1182 60 MAX1198 max1180 100 max1196* max1186 40, multiplexed * future product, please contact factory for availability.
MAX1198 dual, 8-bit, 100msps, 3.3v, low-power adc with internal reference and parallel outputs maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 22 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2002 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 48l,tqfp.eps

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